Cool electronics: just add water

This article originally appeared on fibresystem.org.

We’ve all been taught that electronics and water don’t mix, but researchers at IBM’s Zurich Research Laboratory say that doesn’t have to be the case. In fact, they are proposing that tiny rivers of water be used to cool three-dimensional stacks of silicon chips in future generations of server processors and communications ICs.

Not only would this enhance the performance of the silicon, the heat harvested from the chips could be piped into heating and hot water systems to create the ultimate “green” data centre.

To this end, IBM researchers in collaboration with the Fraunhofer Institute in Berlin have demonstrated a prototype that integrates a cooling system into a 3D chip by piping pressurized water between each layer in the stack.

So-called 3D chip stacks — which take chips and memory devices that traditionally sit side-by-side on a silicon wafer and stack them together on top of one another — represent one of the most promising approaches to enhancing chip performance beyond its predicted limits.

These limits are expected to arise as chip makers pack more processing power onto a chip by scaling down the transistors — following the well-known Moore’s Law.

First, there’s the fact that the wiring between chips does not scale with the transistors on them, because the width of wires is shrinking but their length is not. 3D chip stacks exploit the third dimension to create much shorter vertical connections between the chips in each layer — up to 1000 times shorter according to IBM.

Using 3D chip stacks alleviates the wiring crisis but introduces another problem — cooling. IBM estimates that a 3D chip stack with an area of 4 cm and a thickness of about 1 mm would generate close to 1 kW in heat — more than enough to melt the components.

Conventional coolers attached to the back of a chip simply don’t scale to meet this requirement. What’s more, the 3D stacking process exacerbates the problem because each layer poses an additional barrier to heat removal.

“In order to exploit the potential of high-performance, 3D chip stacking, we need interlayer cooling,” explains Thomas Brunschwiler, project leader at IBM’s Zurich Research Laboratory. “Until now, nobody has demonstrated viable solutions to this problem.”

The key technical challenge was to design a system that maximizes the water flow through the layers, yet hermetically seals the interconnects to prevent water from causing electrical shorts. IBM researchers packaged the chip stacks in a sealed pressurized silicon housing with an inlet reservoir on one side and an outlet reservoir on the other. The cooling layer in the prototype was just 100 µm thick and contained 10,000 vertical interconnects per cm2.

IBM says the complexity of such a system resembles that of a human brain, wherein millions of nerves and neurons for signal transmissions are intermixed but do not interfere with tens of thousands of blood vessels for cooling and energy supply. IBM hopes to commercialize the technology in the next five years.

Reproduced with permission. © Institute of Physics and IOP Publishing Ltd.